The present invention relates to the field of semiconductor device fabrication; more specifically, it relates to a method fabricating a trench and a trench capacitor having buried dielectric collars.
One use for trench capacitors is for the storage node of dynamic random access memory (DRAM) cells. In such applications there are parasitic sidewall leakage currents from a bitline of the DRAM cell to the storage node and from the storage node to the substrate. Buried dielectric collars are used to reduce these leakages. However, present schemes for forming buried collars are limited in the width of the collar formed (and thus limit leakage reduction) and are difficult to scale as trench widths decrease. Therefore, there is a need for a scalable buried dielectric collar process and reduced leakage trench capacitor using a buried dielectric collar.